中圖分類號：TN919.8 文獻標志碼：A DOI: 10.16157/j.issn.0258-7998.245853
中文引用格式： 付強，喬輝，楊飛虎，等. 基于FPGA的多路SGMII接口以太網(wǎng)設(shè)計與測試[J]. 電子技術(shù)應(yīng)用，2025，51(2)：75-80.
英文引用格式： Fu Qiang，Qiao Hui，Yang Feihu，et al. The design and test of Ethernet with multiple SGMII based on FPGA[J]. Application of Electronic Technique，2025，51(2)：75-80.

The design and test of Ethernet with multiple SGMII based on FPGA

Abstract： Due to power consumption, size, and cost constraints, embedded processors typically integrate one or two Ethernet controllers, which cannot meet the demand for simultaneous transmission of multiple Ethernet data streams in certain specific field applications. This paper proposes an Ethernet design based on Field-Programmable Gate Array(FPGA), leveraging the high-speed and parallel processing advantages of FPGA, and the integrated Serializer/Deserializer(SerDes) resources to extend multiple Ethernet interfaces for simultaneous data transmission and reception. Communication with external PHY chips uses the Serial Gigabit Media Independent interface(SGMII), which can effectively reduce PCB size and wiring complexity. A multi-level testing method for the reliability of the underlying link transmission is proposed. Finally, through on-board debugging and verification, the 12 Ethernet interfaces achieve stable transmission at 1 000 Mb/s with no data errors.

Key words : FPGA；SGMII；Ethernet；PHY