摘要： 在SIP（System In a Package）系統(tǒng)中集成具有LVDS（Low-Voltage Differential Signal）接口的多通道高速模數(shù)轉(zhuǎn)換器（Analog-to-Digital Converter，ADC）時，面臨不同LVDS輸出通道延時不同所導致的數(shù)據(jù)采集錯誤的問題，為此設計了一個多通道自適應LVDS接收器。通過采用數(shù)據(jù)時鐘恢復技術產(chǎn)生一個多相位的采樣時鐘，并結(jié)合ADC的測試模式來確認每一個通道的采樣相位，能夠自動對每一個通道的延時分別進行調(diào)整，以達到對齊各通道采樣相位點，保證數(shù)據(jù)正確采集的目的。最后，基于先進CMOS工藝進行了接收器的設計、仿真、后端設計實現(xiàn)和流片測試，仿真和流片后的板級測試結(jié)果均表明該接收器能夠?qū)νǖ姥舆t進行自動調(diào)節(jié)以對齊采樣相位，且最大的采樣相位調(diào)節(jié)范圍為±3 bit，信噪比大于65 dB，滿足了設計要求和應用需求。
1.CETC Suntai Information Technology Co.，Ltd.； 2.No. 58 Research Institute， CETC
Abstract： When integrating multi-channel high-speed ADC (Analog-to-Digital Converter) with LVDS (Low Voltage Differential Signal) interface in SIP (System In a Package) system, it is faced with the problem of clock-to-data skew, data-to-data skew, accumulated clock jitter and so on caused by different LVDS channel with different delays. Therefore, a multi-channel LVDS receiver was designed in this paper which can adaptively adjust the skew of each LVDS channel. The receiver uses data clock recovery technology to generate eight multi-phase sampling clocks, combining with ADC test mode to confirm the sampling phase of each channel, the delay of each channel can be automatically adjusted, aiming to align the sampling phase of channels and ensure the data correct. Finally, the receiver was designed, simulated, and realized based on advanced CMOS technology. The results of simulation and chip test show that the receiver can automatically adjust the delay of each channel to align the sampling phase, the maximum range of sampling phase adjustment is ± 3 bit, and the signal-to-noise ratio is greater than 65 dB, which meets the design requirements and application requirements.
Key words : analog-to-digital converter（ADC）；multi-channels LVDS；phase locked loop；clock data recover
本文基于一個多通道信號處理系統(tǒng)的需求，選用了一款LVDS輸出接口、精度為16位的四通道ADC，其最高采樣速率可達125 MS/s。由于通道數(shù)目多，采用SIP（System In a Package）封裝后，LVDS各通道之間的時序誤差比較嚴重，尤其在高低溫環(huán)境下更是明顯，這些均加重了后續(xù)電路采樣時的設計難度，為此需要研究多通道LVDS的數(shù)據(jù)接收技術，確保系統(tǒng)正常接收ADC的數(shù)據(jù)。本文設計了一款基于先進CMOS工藝的多通道LVDS接收單元，以便集成入SoC（System on Chip），實現(xiàn)處理器對ADC數(shù)據(jù)的讀取和處理。
