中圖分類號： TN919；TP274
文獻標識碼： A
DOI：10.16157/j.issn.0258-7998.201076
中文引用格式： 畢彥峰，李杰，胡陳君. 基于FPGA的LVDS無時鐘數(shù)據(jù)傳輸方案設計與實現(xiàn)[J].電子技術應用，2021，47(6)：62-66.
英文引用格式： Bi Yanfeng，Li Jie，Hu Chenjun. Design and implementation of LVDS clockless data transmission scheme based on FPGA[J]. Application of Electronic Technique，2021，47(6)：62-66.

Design and implementation of LVDS clockless data transmission scheme based on FPGA

Abstract： Aiming at the miniaturization requirements of off-line bomb-borne data acquisition and storage equipment, an FPGA-based LVDS clockless high-speed data transmission system is designed. Without an external interface chip, the onboard clock is used to replace the differential clock, and only a pair of differential pins can complete a LVDS clockless data transmission. When there are many data interfaces in the system, the board volume can be greatly reduced. The problem of phase detector failure is solved by increasing the deserialization ratio of the FPGA internal SERDES and 8B/10B encoding of the data, so to provide accurate phase information for the onboard clock to align the serial data and the analog clock. Finally，following the analog clock，the serial LVDS data is deserialized, so as to achieve the purpose of replacing the LVDS accompanying clock with the onboard clock, so as to achieve high-speed LVDS transmission based on FPGA without accompanying clock. Tests show that the system can work reliably and effectively, and has certain engineering practical value.

Key words : FPGA；no clock transmission；LVDS；SERDES