中圖分類號(hào)：TN402 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.234273
中文引用格式： 方俊杰，吳澤一，黃煜蕭，等. 基于FPGA的晶圓級(jí)芯片封裝圖像序列配準(zhǔn)方法的設(shè)計(jì)與實(shí)現(xiàn)[J]. 電子技術(shù)應(yīng)用，2023，49(12)：90-97.
英文引用格式： Fang Junjie，Wu Zeyi，Huang Yuxiao，et al. Method of image sequence registration for wafer level chip scale packaging based on FPGA[J]. Application of Electronic Technique，2023，49(12)：90-97.

Method of image sequence registration for wafer level chip scale packaging based on FPGA

Abstract： The Wafer Level Chip Scale Packaging (WLCSP) of chips on 12-inch wafers without dicing poses significant technological challenges for automatic optical inspection (AOI) in terms of high-quality imaging and imaging speed. To achieve high-quality and high-speed registration of the image sequence, a local image sequence generated by multiple scans needs to be stitched together to form a global image of the wafer. To this end, a phase correlation method based on the four-neighborhood checkerboard registration is implemented using OpenCL in an FPGA to address the challenge. Initially, a two-dimensional Fast Fourier Transform (FFT) and cross-power spectrum function kernel are constructed. Then, dual-port and row-buffered device global memory are employed to reuse the computed spectral data and to apply kernel channel cascading to enhance the registration speed. Finally, the registration result is optimized using a minimum spanning tree algorithm to reduce the cumulative error of global image coordinate calculation. The proposed registration algorithm and its accelerated performance are verified using actual scanned images.

Key words : wafer level chip scale package；image registration；FPGA；OpenCL